This invention relates to a so-called amplification type solid-state imaging device having a potential detecting circuit for each unit cell and a high-speed readout method thereof and more particularly to a solid-state imaging device which is operated at high speed while suppressing a lowering in the signal-noise ratio (S/N ratio).
Recently, solid-state imaging devices which are called amplification type solid-state imaging devices each having a potential detecting circuit for each unit cell are actively developed. In comparison with a CCD type solid-state imaging device conventionally used, since the charge transfer operation is effected only in an area around the photodiodes in this type of solid-state imaging device, the power and voltage required for the charge transfer operation become unnecessary and it is advantageously used for mobile applications in which it is driven by a battery or the like. In this case, however, there occurs a problem that the S/N ratio is lowered by a variation in the characteristic of the potential detecting circuit provided for each unit cell and studies on this matter are actively continued.
FIG. 1 shows the schematic construction of the in amplification type solid-state imaging device. In FIG. 1, an example of the solid-state imaging device Ad having two photodiodes arranged in each unit cell is shown.
In an imaging area on a semiconductor substrate, unit cells are arranged in a two-dimensional fashion. More precisely, the unit cells are arranged in i rows and j columns, where i and j are integers. Of these unit cells, six representive ones are illustrated in FIG. 1. The six unit cells P are arranged in two adjacent rows m and m+1 and three adjacent columns n−1, n and n+1; they are located at intersections (m, n−1), (m, n), (m, n+1), (m+1, n−1), (m+1, n) and (m+1, n+1).
An address pulse line LADi, first and second readout pulse lines LR1i, LR2i and reset pulse line LRSi are arranged in the horizontal direction for each pixel row of the unit cells P(i,j). The unit cells P(i,j) are supplied with an address pulse φADi, first and second readout pulses φR1i, φR2i, and reset pulse φRSi from a pulse generating section 20 via the address pulse line LADi, first and second readout pulse lines LR1i, LR2i and reset pulse line LRSi.
Further, a vertical signal line Sj is provided in the vertical direction for each column of the unit cells P(i,j). A current source Ij is provided between one end of each of the vertical signal lines Sj and the ground node. The other end of each vertical signal line Sj is connected to one end of the current path of a shift transistor (shift gate) SRj. The gates of the shift transistors SHj are commonly connected to a shift pulse line LSH.
One electrode of each coupling capacitor (capacitance) CAj is connected to the other end of the current path of the shift transistor SHj and the current path of a horizontal readout transistor (horizontal readout gate) Hj is connected between the other electrode of a corresponding one of the capacitors CAj and a horizontal signal line 24. The gate of the horizontal readout transistor Hj is connected to a corresponding one of horizontal readout pulse lines LHj. A capacitor which is equivalently represented by a capacitor 25 is associated with the horizontal signal line 24.
Charge storage capacitors (capacitances) CBj are respectively connected between the other electrodes of the capacitors CAj and the ground node. The current paths of clamping transistors (clamping gates) CLPj for offset elimination are respectively connected between connection nodes of the capacitors CAj and CBj and the positive terminal of a clamping DC power supply 23. The gates of the transistors CLPj are connected to a clamp line LCLP.
The shift transistor SHj, capacitors CAj, CBj and clamping transistor CLPj constitute a noise canceller circuit.
A pulse generating section 21 supplies a shift pulse φSH to the gates of the shift transistors SHj via the shift pulse line LSH and supplies a clamp pulse φCLP to the gates of the clamping transistors CLPj via the clamp pulse line LCLP to control the operations thereof.
Further, a pulse generating section 22 respectively supplies horizontal readout pulses φHj to the gates of the horizontal readout transistors Hj via the horizontal readout pulse lines LHj and supplies a clear pulse φCR to the gate of a potential resetting transistor (potential resetting gate) 28 via a clear pulse line LCR. The potential resetting transistor 28 is used for resetting the potential of the capacitor (capacitance) 25, and one end of the current path thereof is connected to the positive terminal of a DC power supply 29 for generating a potential at the reset time and the other end of the current path thereof is connected to the horizontal signal line 24. The voltage value (which is indicated by Vb) of the DC power supply 29 is determined by taking the characteristic of an output buffer circuit 26 into consideration and the clear pulse φCR is supplied to the gate of the transistor 28 to set the potential of the capacitor 25 to the potential Vb before the horizontal readout pulses φHj are supplied.
The horizontal signal line 24 is connected to the input terminal of the output buffer circuit 26 for detecting the potential of the horizontal signal line 24, subjecting the potential to impedance conversion and outputting the potential to the exterior. The output end of the output buffer circuit 26 is connected to an output terminal 27.
Next, the internal construction of the unit cell P(i,j) is explained. In FIG. 1, the unit cell P(m, n−1) is taken as an example and shown in detail, but the other unit cells are also constructed in the same manner. Each unit cell P(i,j) includes photodiodes 1—1, 1-2, readout transistors (readout gates) 2-1, 2—2, reset transistor (reset gate) 4, potential detecting transistor (potential detecting gate) 5, address transistor (address gate) 6 and the like.
The anodes of the photodiodes 1—1, 1-2 are grounded and the cathodes thereof are respectively connected to one-side ends of the current paths of the readout transistors 2-1, 2—2. The other ends of the current paths of the readout transistors 2-1, 2—2 are connected to a storage node 3 (common charge detecting section) in which charges read out from the photodiodes 1—1, 1-2 are temporarily stored and the gates thereof are respectively connected to the readout pulse lines LR1i, LR2i. The reset transistor 4 is connected between the storage node 3 and a power supply 7 and the gate of the reset transistor 4 is connected to a corresponding one of the reset pulse lines LRSi. One end of the current path of the potential detecting transistor 5 is connected to a corresponding one of the vertical signal lines Sj via the output line. 8 of the corresponding unit cell P(i,j) and the gate thereof is connected to the storage node 3. The potential detecting transistor 5 is used for detecting the charges transferred to the storage node 3 and transmits a potential corresponding to an amount of detected charges to the vertical signal line Sj via the output line 8. The current path of the address transistor 6 is connected between the other end of the current path of the potential detecting transistor 5 and the power supply 7 and the gate thereof is connected to the address pulse line LADi. The address transistor 6 is used for activating the potential readout operation for the corresponding unit cell P(i,j). In FIG. 1, in order to clarify the drawing, power supply lines are omitted.
With the above construction, part of the circuit elements of the unit cell can be commonly used for the photodiodes 1—1, 1-2 and the integration density can be enhanced. However, since the symmetry of the circuit arrangement and pattern arrangement of the surrounding portions of the photodiodes 1—1, 1-2 cannot be maintained, the tolerance for the mask alignment in the manufacturing process becomes severe. That is, the manufacturing technique and the integration density are set in the trade-off relation.
Next, the operation of the amplification type solid-state imaging device shown in FIG. 1 is explained with reference to the timing charts shown in FIGS. 2 and 3. FIG. 2 shows pulse timings for driving the amplification type solid-state imaging device and FIG. 3 shows the relation between the horizontal readout pulses φH1, φH2, φH3, . . . and the clear pulse φCR.
In FIGS. 2 and 3, a standard television system is assumed. In FIG. 2, HBLK indicates a horizontal sync. pulse and the high-level period is a horizontal scanning retrace interval. The low-level period of the horizontal sync. pulse HBLK is a horizontal effective scanning period and a horizontal readout pulse φHj is generated during this period. The horizontal scanning retrace interval and the horizontal effective scanning period constitute one horizontal scanning period (1H). In the horizontal scanning period, each signal readout operation from each of the unit cells is effected during the horizontal scanning retrace interval and the readout signal is stored in the capacitor CBj in the form of charges. After this, the horizontal readout transistors Hj are sequentially turned ON in the horizontal effective scanning period to connect the capacitor 25 in parallel with the capacitors CAj, CBj, thereby reading out the stored signal charges. The signal readout operation in this period is commonly effected for the unit cells arranged in the horizontal direction.
Next, the above readout operation is explained in more detail by taking the photodiodes 1—1 of the unit cell P(m, n−1) as an example. Charges created by photoelectrically converting light incident on the photodiode 1—1 are stored in the photodiode 1—1 until the readout transistor 2-1 is turned ON. The operation which is first effected in the horizontal scanning retrace interval is to set the address pulse φADm to the high level so as to turn ON the address transistor 6 (t=t0) and construct a source-follower circuit by use of the vertical signal line Sn-1, current source In-1 and potential detecting transistor 5 so that the charge of the storage node 3 can be detected by use of the potential detecting transistor 5. As a result, only a potential corresponding to the charge amount of the storage node 3 and determined by the gate potential of the potential detecting transistor 5 is transmitted to the vertical signal line Sn-1.
Further, a dark current integrated value stored in the storage node 3 can be discharged by setting the reset pulse φRSm to the high level to turn ON the reset transistor 4 at the beginning of the horizontal scanning retrace interval. Thus, the storage node 3 can be set at the power supply voltage value (which is denoted by Vdd).
It is now assumed that the capacitance of the storage node 3 is Cij when the charge Q is transferred from the photodiode 1—1 to the storage node 3. Then, the potential V3 of the storage node 3 can be expressed by the following equation (1).V3=Vdd+Q/Cij  (1)
where Vdd is a power supply voltage.
When the above value is detected by the potential detecting transistor 5, the potential V8 of the output line 8 takes a value expressed by the following equation (2).                                                         V8              =                            ⁢                              mV3                +                V0                                                                                        =                            ⁢                                                m                  ⁡                                      (                                          Vdd                      +                                              Q                        /                        Cij                                                              )                                                  +                V0                                                                                        =                            ⁢                                                mQ                  /                  Cij                                +                mVdd                +                V0                                                                        (        2        )            
where m is the modulation degree of the transistor and V0 is an offset voltage determined by variations in the current source In-1 and the threshold voltage of the potential detecting transistor 5.
In the present manufacturing technology, the modulation degree m can be suppressed to a small variation for the entire surface of the wafer, but the offset voltage V0 cannot be always suppressed to a small variation and is considered as an amount which varies depending on the vertical signal lines. Therefore, the modulation degree m can be regarded as being constant, but it is necessary to correct the offset voltage V0. The correction is made in the next operation.
The potential V8 of the output line 8 and the potential VA of a node NA which is a connection node of the capacitors CAj and CBj in the noise canceller circuit are considered while it is assumed that the potential of the DC power supply 23 is Vref. It is supposed that V8 is expressed by the following equation (3) at the time t=t1 immediately after the resetting operation.V8=mVdd+V0=V1  (3)
After this, at the time t=t2 immediately after application of the clamp pulse φCLP, the potential V8 of the output line 8 is kept at V1, but VA is set to a value expressed as follows.
 VA=Vref  (4)
That is, a potential difference (Vref−V1) appears across the capacitor CAn-1. The potential of the electrode of the capacitor CBn-1 opposite to the electrode thereof which is grounded is set to a potential of Vref. Next, the readout pulse φR1m is set to the high level to turn ON the readout transistor 2-1 so that the charge Q stored in the photodiode 1—1 can be transferred to the storage node 3. As a result, at the time t=t3, V8 is set to the following value.V8=mQ/Cij+V1  (5)
Therefore, the potential VA of the node NA is set to a voltage expressed by the following equation (6).VA=Vref+mQ/Cij·CAj/(CAj+CBj)  (6)
After this, the shift pulse φSH is set to the low level to turn OFF the shift transistor SHn-1 and separate the vertical signal line Sn-1. If charges stored in the capacitor 25 and capacitor CBj in this state (t=t4) are respectively indicated by Q1, Q2 and when the capacitance of the capacitor 25 is CH and the voltage value of the DC power supply 29 is Vb, then the charges Q1, Q2 are expressed by the following equations (7) and (8).Q1=CH·Vb  (7)Q2=CBjVref+mQ/Cij·CAjCBj/(CAj+CBj)  (8)
If the horizontal readout pulse φHn-1 is set to the high level to turn ON the horizontal readout transistor Hn-1, the capacitors are connected in parallel and the potential of the horizontal signal line 24 is set to a value expressed by the following equation (9).                                           (                          Q1              +              Q2                        )                    /                      (                          CH              +              CBj                        )                          =                                            (                                                CH                  ·                  Vb                                +                CBjVref                            )                        /                          (                              CH                +                CBj                            )                                +                                    mQ              /              Cij                        ·                          CAjCBj              /                              (                                  CAj                  +                  CBj                                )                                                                        (        9        )            
After this, as shown in the timing chart of FIG. 3, the clear pulse φCR is set to the high level in the low-level period of the horizontal sync. pulse HBLK and then a corresponding one of the horizontal readout pulses φH1, φH2, φH3, . . . is sequentially set to the high level so as to change the potential of the horizontal signal line 24 and thus perform the readout operation.
As is clearly understood from the equation (9), the potential of the horizontal signal line 24 contains a single constituent factor except that it contains the capacitances CAj, CBj as an amount which may vary for each line and Cij which may vary for each unit cell. That is, it does not contain V0 shown in the equation (3) and varying according to the threshold voltage or the like and is effectively corrected based on the value of the potential V8 of the output line 8.
Further, it is understood by specifically studying the equation (9) that the potential is determined not by the absolute values of the capacitances but by the ratios thereof except the item of mQ/Cij. This means that the output voltage is determined not by the absolute value of the film thickness of the gate oxide film, for example, but by the ratio of the geometrical sizes of the patterns of the capacitors and a reduction in the variation can be relatively easily attained by the present manufacturing technology. Since the modulation degree m of the transistor is a relatively easily controllable variable, can be attained with a less variation as described before and can be regarded as being substantially constant, the potential is slightly influenced only by Cij acting as an amount which may vary for each unit cell.
Basically, it is considered to reduce the number of photodiodes used for charge readout in order to drive the solid-state imaging device with the construction as shown in FIG. 1 at high speed.
The operation timings used for attaining the high-speed operation are shown in FIGS. 4 and 5. FIG. 4 shows the operation timing used when only one of the two photodiodes in each unit cell is used for the readout operation. In the operation timing shown in FIG. 4, signal charges are read out only from the photodiode 1—1 and charges stored in the photodiode 1-2 are discharged via the storage node 3 by supplying the readout pulse φR2m in synchronism with the reset pulse φRSm to simultaneously turn ON the reset transistor 4 and readout transistor 2—2. As a result, the readout speed for one frame is enhanced to twice the normal readout speed.
FIG. 5 is a timing chart wherein the same idea is applied to a pixel column, the readout operation is effected only for the even columns without effecting, the readout operation for the odd columns. That is, the horizontal readout pulses φH1, φH3, φH5, . . . for the odd columns are fixed at the low level and the horizontal readout pulses φH2, φH4, φH6, . . . for the even columns are sequentially set to the high level to perform the readout operation. As a result, the readout speed for one frame can be enhanced to twice the normal readout speed.
However, the improvement of the operation speed by the above methods is accompanied by a lowering in the S/N ratio. That is, the S/N ratio may be easily lowered since the number of photodiodes used for the readout operation is reduced to half the number of photodiodes used in the normal driving operation.